Advances in electronic devices generally include reducing the size of the components that form integrated circuits. With smaller circuit components, the value of each unit area (real estate) of a semiconductor wafer becomes higher because of the ability to use more of the wafer area for the integrated circuit components. To properly form an integrated circuit that employs a much higher percentage of useable wafer area, it is critical that contaminants on the semiconductor wafer surface be reduced to levels that are commercially acceptable. In integrated circuit fabrication, a process known as chemical mechanical polish (hereinafter “CMP”) has become popular and is used to achieve flat surface for photolithography patterning. A conventional CMP system incorporates numerous elements for maneuvering the semiconductor wafer such as wafer boats, load cassettes, robotic arms, carriers, and other transportation means. During the traditional CMP process, the semiconductor wafer is exposed to polytetrafluoroethylene (PTFE) or Teflon® manufactured by DuPont and other plastic materials used to form the wafer boats, carriers and handlers and can generate polymeric defects after being exposed to chemicals during the post-CMP cleans, as well as the post Via, Trench and Etch Stop etch cleans. Although the carbon fluorine (C:F) bond found in polytetrafluoroethylene is a particularly strong bond, the PTFE will eventually break down from the physical handling in conjunction with the chemicals used during conventional CMP processes. In addition, wafer handling can also cause physical abrasion between the semiconductor wafer and the PTFE coated carrier devices.
An additional problem is the front edge of the semiconductor wafer may be contaminated subsequently with these defects by contacting the wafer boats or wafer handlers. Importantly, these polymeric defects may be disturbed and scattered all over the front wafer surface during the down stream processing. These defects will then be buried by the following dielectric layered depositions which can cause significant yield loss at each level of interconnection.
In addition, current back wafer cleaning processes typically only remove copper contamination with nitric acid. The current processes are not capable of cleaning non-copper devices and cannot remove the polymer residues derived from the PTFE lining on the carrier devices. PTFE is a combination of carbon and fluoride and is a very tough, uniform material and it is very difficult using normal and conventional chemistries to remove polymeric residues derived from PTFE. In addition, the current back wafer cleaning processes cannot clean the front edge of the wafer held by the carrier devices.
In addition, the prior methods are incapable of dissolving the PTFE defects due to the high chemical stability of the carbon fluorine bond.